In a multiprocessor system, the processors must be able to communicate among one another under many circumstances, to assure a certain coherence of operation. To do so, means are provided that enable dialog between any two processors. The processor that initiates the dialog then issues a request to another addressee processor, which sends an acknowledgement intended for the originator to indicate that it has taken the request into account. Then, in response to the request received, the receiving processor is generally made to interrupt the operations it is running before the request was received. This dialog between processors makes it possible to employ what is typically known as an interrupt mechanism.
Dialog between processors occurs under numerous circumstances in the course of operation of the system. The set of these possibilities can be subdivided into two categories: selective requests, where an originating processor addresses a request to a particular addressee processor; global requests, where a processor addresses a request to all the other processors of the system simultaneously.
Generally, requests are sent in the course of the execution of particular operations by the originating processor, and the accomplishment of these operations is on the condition of the reception of acknowledgements from the addressee processors. As a result, an operation that requires sending requests includes a phase of monitoring the acknowledgements received.
To this end, one conventional solution comprises interrupting the ongoing operation for each request, in order to monitor reception of the corresponding acknowledgement. This solution, which is the simplest, is valuable in cases where the order of acceptance by the addressee processors must be the same as that in which the corresponding requests were sent. Quite often, however, such synchronization of the recipient processors is unnecessary, and the only important factor is that the recipient processors have effectively accepted their respective requests. In that case, the conventional solution mentioned above is not optimal in terms of system performance. In fact, the time interval between sending of a request and the instant when the acknowledgement is received may be relatively long, because the addressee processor may be in the process of running a long operation at the time the request is sent that cannot be interrupted. Only after this operation is completely finished, can the request be accepted and the acknowledgement sent. During this entire period of time, the originating processor is in a waiting state. The degradation in system performance is limited, however, if the number of multiple requests for any operation is in turn limited, which is the case if the number of processors in the system is itself limited. On the other hand, in systems that include a large number of processors, the reduction in performance is not insignificant, particularly in the case of operations involving distributing processes to processors (often called "dispatching"), which are triggered more often, the higher the number of processors.